During 2001, a group of companies called the Arapahoe Work Group (led primarily by Intel) developed a draft of a new high-speed bus specification code named 3GIO (third-generation I/O).

In August 2001, the PCI Special Interest Group (PCI-SIG) agreed to take over, manage, and promote the 3GIO architecture specification as the future generation of PCI. In April 2002, the 3GIO draft version 1.0 was completed, transferred to the PCI-SIG, and renamed PCI Express. Finally in July 2002, the PCI Express 1.0 specification was approved.

The original 3GIO code name was derived from the fact that this new bus specification was designed to initially augment and eventually replace the previously existing ISA/AT-Bus (first-generation) and PCI (second-generation) bus architectures in PCs.

Each of the first two generations of PC bus architectures was designed to have a 10- to 15-year useful life in PCs. In being adopted and approved by the PCI-SIG, PCI Express is now destined to be the dominant PC bus architecture designed to support the increasing bandwidth needs in PCs over the next 10–15 years.

The key features of PCI Express are as follows:

• Compatibility with existing PCI enumeration and software device drivers.

• Physical connection over copper, optical, or other physical media to allow for future encoding schemes.

• Maximum bandwidth per pin allows small form factors, reduced cost, simpler board designs and routing, and reduced signal integrity issues.

• Embedded clocking scheme enables easy frequency (speed) changes as compared to synchronous clocking.

• Bandwidth (throughput) increases easily with frequency and width (lane) increases.

• Low latency suitable for applications requiring isochronous (time-sensitive) data delivery, such as streaming video.

• Hot plugging and hot swapping capabilities.

• Power management capabilities.

PCI Express is another example of how the PC is moving from parallel to serial interfaces. Earlier generation bus architectures in the PC have been of a parallel design, in which multiple bits are sent simultaneously over several pins in parallel. The more bits sent at a time, the faster the bus throughput is.

The timing of all the parallel signals must be the same, which becomes more and more difficult to do over faster and longer connections. Even though 32 bits can be transmitted simultaneously over a bus such as PCI or AGP, propagation delays and other problems cause them to arrive slightly skewed at the other end, resulting in a time difference between when the first and last of all the bits arrive.

A serial bus design is much simpler, sending 1 bit at a time over a single wire, at much higher rates of speed than a parallel bus would allow. By sending the bits serially, the timing of individual bits or the length of the bus becomes much less of a factor.

By combining multiple serial data paths, even faster throughputs can be realized that dramatically exceed the capabilities of traditional parallel buses. PCI Express is a very fast serial bus design that is backward-compatible with current PCI parallel bus software drivers and controls.

In PCI Express, data is sent full duplex (simultaneously operating one-way paths) over two pairs of differentially signaled wires called a lane. Each lane allows for about 250MBps throughput in each direction initially, and the design allows for scaling from 1 to 2, 4, 8, 16, or 32 lanes.

For example, a high-bandwidth configuration with 8 lanes allowing 8 bits to be sent in each direction simultaneously would allow up to 2,000MBps bandwidth (each way) and use a total of only 40 pins (32 for the differential data pairs and 8 for control).

Future increases in signaling speed could increase that to 8,000MBps each way over the same 40 pins. This compares to PCI, which has only 133MBps bandwidth (one way at a time) and requires more than 100 pins to carry the signals. For expansion cards, PCI Express will take on the physical format of a smaller connector that appears adjacent to any existing PCI slots on the motherboard.

PCI Express uses an IBM-designed 8-bit–to–10-bit encoding scheme, which allows for self-clocked signals that will easily allow future increases in frequency. The starting frequency is 2.5GHz, and the specification will allow increasing up to 10GHz in the future, which is about the limit of copper connections.

By combining frequency increases with the capability to use up to 32 lanes, PCI Express will be capable of supporting future bandwidths up to 32GBps. PCI Express is designed to augment and eventually replace many of the buses currently used in PCs.

It will not only be a supplement to (and the eventual replacement for) PCI slots, but can also be used to replace the existing Intel hub architecture, HyperTransport, and similar high-speed interfaces between motherboard chipset components.

Additionally, it will replace video interfaces such as AGP and act as a mezzanine bus to attach other interfaces, such as Serial ATA, USB 2.0, 1394b (FireWire or iLink), Gigabit Ethernet, and more.

Because PCI Express can be implemented over cables as well as onboard, it can be used to create systems constructed with remote "bricks" containing the bulk of the computing power.

Imagine the motherboard, processor, and RAM in one small box hidden under a table, with the video, disk drives, and I/O ports in another box sitting out on a table within easy reach. This will enable a variety of flexible PC form factors to be developed in the future without compromising performance.

PCI Express will not replace PCI or other interfaces overnight. System developers will continue to integrate PCI, AGP, and other bus architectures into system designs for several more years. Just as with PCI and the ISA/AT-Bus before, there will likely be a long period of time during which both buses will be found on motherboards.

Gradually, though, fewer PCI and more PCI Express connections will appear. Over time, PCI Express will eventually become the preferred general-purpose I/O interconnect over PCI. I expect the move to PCI Express will be similar to the transition from ISA/AT-Bus to PCI during the 1990s.

Note that I'm including this information on PCI Express well in advance of it actually appearing in PCs. In other words, don't hold your breath because PCI Express is still in the early design stages, and you won't see it in PC motherboards for some time yet.

The PCI-SIG estimates that the first desktop PCs using PCI Express will begin to emerge in mid- to late 2004. After that, PCI Express is expected to appear in portable devices and low-end servers and workstations by late 2004, and in high-end servers and workstations by late 2005.

These are just estimates, of course, and might change according to the dynamics of the industry. The PCI Express Bridge 1.0 and Mini PCI Express Card specifications are designed to help bring PCI Express products into being by using existing PCI technology. These specifications might help shorten the time-to-market for PCI Express products.

For more information on PCI Express, I recommend consulting the PCI-SIG Web site.