Hub Architecture

The newer 800 series chips from Intel use a hub architecture in which the former North Bridge chip is now called a Memory Controller Hub (MCH) and the former South Bridge is called an I/O Controller Hub (ICH).

Rather than connect them through the PCI bus as in a standard North/South Bridge design, they are connected via a dedicated hub interface that is twice as fast as PCI. The hub design offers several advantages over the conventional North/South Bridge design:

  • It's faster. The hub interface is a 4X (quad-clocked) 66MHz 8-bit (4x66MHzx1 byte = 266MBps) interface, which has twice the throughput of PCI (33MHzx32 bits = 133MBps).

  • Reduced PCI loading. The hub interface is independent of PCI and doesn't share or steal PCI bus bandwidth for chipset or Super I/O traffic. This improves performance of all other PCI bus connected devices because the PCI bus is not involved in these transactions.

  • Reduced board wiring. Although twice as fast as PCI, the hub interface is only 8 bits wide and requires only 15 signals to be routed on the motherboard. By comparison, PCI requires no less than 64 signals be routed on the board, causing increased electromagnetic interference (EMI) generation, greater susceptibility to signal degradation and noise, and increased board manufacturing costs.

This hub interface design allows for a much greater throughput for PCI devices because there is no South Bridge chip (also carrying traffic from the Super I/O chip) hogging the PCI bus. Due to bypassing PCI, hub architecture also enables greater throughput for devices directly connected to the I/O Controller Hub (formerly the South Bridge), such as the new higher-speed ATA-100 and USB 2.0 interfaces.

The hub interface design is also very economical, being only 8 bits wide. Although this seems too narrow to be useful, there is a reason for the design. By making the interface only 8 bits wide, it uses only 15 signals, compared to the 64 signals required by the 32-bit-wide PCI bus interface used by North/South Bridge chip designs.

The lower pin count means less circuit routing exists on the board, less signal noise and jitter occur, and the chips themselves have many fewer pins, making them smaller and more economical to produce. Although it transfers only 8 bits at a time, the hub interface executes four transfers per cycle and cycles at 66MHz.

This gives it an effective throughput of 4x66MHzx1 byte = 266MB per second (MBps). This is twice the bandwidth of PCI, which is 32 bits wide but runs only one transfer per 33MHz cycles for a total bandwidth of 133MBps. So, by virtue of a very narrow—but very fast—design, the hub interface achieves high performance with less cost and more signal integrity than with the previous North/South Bridge design.

The MCH interfaces between the high-speed processor bus (533/400/133/100/66MHz) and the hub interface (66MHz) and AGP bus (533/266/133/66MHz), whereas the ICH interfaces between the hub interface (66MHz) and the ATA (IDE) ports (66/100MHz) and PCI bus (33MHz).

The ICH also includes a new low-pin-count (LPC) bus, consisting basically of a stripped 4-bit wide version of PCI designed primarily to support the motherboard ROM BIOS and Super I/O chips. By using the same 4 signals for data, address, and command functions, only nine other signals are necessary to implement the bus, for a total of only 13 signals.

This dramatically reduces the number of traces connecting the ROM BIOS chip and Super I/O chips in a system as compared to the 96 ISA bus signals necessary for older North/South Bridge chipsets that used ISA as the interface to those devices. The LPC bus has a maximum bandwidth of 6.67MBps, which is close to ISA and more than enough to support devices such as ROM BIOS and Super I/O chips.