The speed and performance issue with memory is confusing to some because memory speed is usually expressed in ns (nanoseconds) and processor speed has always been expressed in MHz (megahertz). Recently, however, some newer and faster types of memory have speeds expressed in MHz, adding to the confusion. Fortunately, you can translate one to the other.

A nanosecond is defined as one billionth of a second—a very short time indeed. To put some perspective on that, the speed of light is 186,282 miles (299,792 kilometers) per second in a vacuum. In one billionth of a second, a beam of light travels a mere 11.80 inches or 29.98 centimeters—less than the length of a typical ruler!

Chip and system speed has been expressed in megahertz (MHz), which is millions of cycles per second, or gigahertz (GHz), which is billions of cycles per second. During 2004, systems will exceed 4GHz or 4 billion cycles per second. Because it is confusing to speak in these different terms for speeds, I thought it would be interesting to see how they compare.

The dominant standard in 2000 was to have 100MHz and even 133MHz memory, called PC100 and PC133, respectively. Starting in early 2001, double data rate (DDR) memory of 200MHz and 266MHz become popular, along with 800MHz RDRAM. In 2002 standard 333MHz DDR memory arrived, and in 2003 the speeds increased to 400MHz.

During 2004, we will see the introduction of DDR2 at 400MHz and then 533MHz speeds. System memory timing is a little more involved than simply converting nanoseconds to megahertz. The transistors for each bit in a memory chip are most efficiently arranged in a grid, using a row and column scheme to access each transistor.

All memory accesses involve selecting a row address and then a column address and then transferring the data. The initial setup for a memory transfer where the row and column addresses are selected is a necessary overhead referred to as latency. The access time for memory is the cycle time plus latency for selecting the row and column addresses.

For example, SDRAM memory rated at 133MHz (7.5ns) typically takes five cycles to set up and complete the first transfer (5x7.5ns = 37.5ns) and then perform three additional transfers with no additional setup. Thus, four transfers take a total of eight cycles, or an average of about two cycles per transfer.

Over the development life of the PC, memory has had a difficult time keeping up with the processor, requiring several levels of high-speed cache memory to intercept processor requests for the slower main memory.

Generally, things work best when the throughput of the memory bus matches the throughput of the processor bus. Compare the memory bus transfer speeds (bandwidth) to the speeds of the processor bus.

Because the processor is fairly well insulated from directly dealing with main memory by the L1 and L2 cache, memory performance has often lagged behind the performance of the processor bus.

More recently, however, systems using SDRAM, DDR SDRAM, and RDRAM have memory bus performance equaling that of the processor bus. When the speed of the memory bus equals the speed of the processor bus, memory performance is optimum for that system.

Fast Page Mode DRAM

Standard DRAM is accessed through a technique called paging. Normal memory access requires that a row and column address be selected, which takes time. Paging enables faster access to all the data within a given row of memory by keeping the row address the same and changing only the column.

Memory that uses this technique is called Page Mode or Fast Page Mode memory. Other variations on Page Mode were called Static Column or Nibble Mode memory. Paged memory is a simple scheme for improving memory performance that divides memory into pages ranging from 512 bytes to a few kilobytes long.

The paging circuitry then enables memory locations in a page to be accessed with fewer wait states. If the desired memory location is outside the current page, one or more wait states are added while the system selects the new page. To improve further on memory access speeds, systems have evolved to enable faster access to DRAM.

One important change was the implementation of burst mode access in the 486 and later processors. Burst mode cycling takes advantage of the consecutive nature of most memory accesses.

After setting up the row and column addresses for a given access, using burst mode, you can then access the next three adjacent addresses with no additional latency or wait states. A burst access usually is limited to four total accesses. To describe this, we often refer to the timing in the number of cycles for each access.

A typical burst mode access of standard DRAM is expressed as x-y-y-y; x is the time for the first access (latency plus cycle time), and y represents the number of cycles required for each consecutive access. Standard 60ns DRAM normally runs 5-3-3-3 burst mode timing.

This means the first access takes a total of five cycles (on a 66MHz system bus, this is about 75ns total or 5x15ns cycles), and the consecutive cycles take three cycles each (3x15ns = 45ns). As you can see, the actual system timing is somewhat less than the memory is technically rated for.

Without the bursting technique, memory access would be 5-5-5-5 because the full latency is necessary for each memory transfer. DRAM memory that supports paging and this bursting technique is called Fast Page Mode (FPM) memory. The term comes from the capability of memory accesses to data on the same page to be done with less latency. Most 486 and Pentium systems from 1995 and earlier use FPM memory.

Another technique for speeding up FPM memory was called interleaving. In this design, two separate banks of memory are used together, alternating access from one to the other as even and odd bytes. While one is being accessed, the other is being precharged, when the row and column addresses are being selected.

Then, by the time the first bank in the pair is finished returning data, the second bank in the pair is finished with the latency part of the cycle and is now ready to return data. While the second bank is returning data, the first bank is being precharged, selecting the row and column address of the next access.

This overlapping of accesses in two banks reduces the effect of the latency or precharge cycles and allows for faster overall data retrieval. The only problem is that to use interleaving, you must install identical pairs of banks together, doubling the amount of SIMMs or DIMMs required.

This method was popular on 32-bit wide memory systems on 486 processors but fell out of favor on Pentiums because of their 64-bit wide memory widths. To perform interleaving on a Pentium machine, you would need to install memory 128 bits at a time, meaning four 72-pin SIMMs or two DIMMs at a time.

Extended Data Out RAM

In 1995, a newer type of memory called extended data out (EDO) RAM became available for Pentium systems. EDO, a modified form of FPM memory, is sometimes referred to as Hyper Page mode. EDO was invented and patented by Micron Technology, although Micron licensed production to many other memory manufacturers.

EDO memory consists of specially manufactured chips that allow a timing overlap between successive accesses. The name extended data out refers specifically to the fact that unlike FPM, the data output drivers on the chip are not turned off when the memory controller removes the column address to begin the next cycle.

This enables the next cycle to overlap the previous one, saving approximately 10ns per cycle. The effect of EDO is that cycle times are improved by enabling the memory controller to begin a new column address instruction while it is reading data at the current address.

This is almost identical to what was achieved in older systems by interleaving banks of memory, but unlike interleaving, with EDO you didn't need to install two identical banks of memory in the system at a time. EDO RAM allows for burst mode cycling of 5-2-2-2, compared to the 5-3-3-3 of standard fast page mode memory.

To do four memory transfers, then, EDO would require 11 total system cycles, compared to 14 total cycles for FPM. This is a 22% improvement in overall cycling time, but in actual testing, EDO typically increases overall system benchmark speed by about 5%.

Even though the overall system improvement might seem small, the important thing about EDO was that it used the same basic DRAM chip design as FPM, meaning that there was practically no additional cost over FPM. In fact, in its heyday, EDO cost less than FPM and yet offered higher performance. EDO RAM generally comes in 72-pin SIMM form.

To actually use EDO memory, your motherboard chipset must support it. Most motherboard chipsets on the market from 1995 (Intel 430FX) through 1997 (Intel 430TX) offered support for EDO.

Because EDO memory chips cost the same to manufacture as standard chips, combined with Intel's support of EDO in all its chipsets, the PC market jumped on the EDO bandwagon full force.

EDO RAM was ideal for systems with bus speeds of up to 66MHz, which fit perfectly with the PC market up through 1997. However, since 1998 with the advent of faster system bus speeds (100MHz and above), the market for EDO has rapidly declined as the newer and faster SDRAM architecture has become the standard for new PC system memory.

A variation of EDO is burst EDO (BEDO). BEDO is basically EDO memory with special burst features for even speedier data transfers than standard EDO. Unfortunately, the technology was owned by Micron and not a free industry standard, so only one chipset (Intel 440FX Natoma) ever supported it.

BEDO was therefore quickly overshadowed by industry-standard SDRAM, which was favored among PC system chipset and system designers over proprietary designs. As such, BEDO never really saw the light of production, and to my knowledge no systems ever really used it.