Rambus DRAM (RDRAM) is a fairly radical memory design found in high-end PC systems from late 1999 through 2002. Intel signed a contract with Rambus in 1996 ensuring it would support RDRAM into 2001.

After 2001, Intel continued to support RDRAM in existing systems, but new chipsets and motherboards primarily shifted to DDR SDRAM, and all future Intel chipsets and motherboards are being designed for either conventional DDR or the new DDR2 standard.

RDRAM standards had been proposed that will support faster processors through 2006; however, without Intel's commitment to future chipset development and support, very few RDRAM-based systems have been sold in 2003. Due to the lack of industry support from chipset and motherboard manufacturers, RDRAM will most likely not play a big part in future PCs.

With RDRAM, Rambus developed what is essentially a chip-to-chip memory bus, with specialized devices that communicate at very high rates of speed. What might be interesting to some is that this technology was first developed for game systems and first made popular by the Nintendo 64 game system, and it subsequently was used in the Sony Playstation 2.

Conventional memory systems that use FPM/EDO or SDRAM are known as wide-channel systems. They have memory channels as wide as the processor's data bus, which for the Pentium and up is 64 bits. The dual inline memory module (DIMM) is a 64-bit wide device, meaning data can be transferred to it 64 bits (or 8 bytes) at a time.

RDRAMs, on the other hand, are narrow-channel devices. They transfer data only 16 bits (2 bytes) at a time (plus 2 optional parity bits), but at much faster speeds. This is a shift away from a more parallel to a more serial design and is similar to what is happening with other evolving buses in the PC.

16-bit single channel RIMMs originally ran at 800MHz, so the overall throughput is 800x2, or 1.6GB per second for a single channel—the same as PC1600 DDR SDRAM. Pentium 4 systems typically used two banks simultaneously, creating a dual-channel design capable of 3.2GBps, which matches the bus speed of the original Pentium 4 processors.

The RDRAM design features less latency between transfers because they all run synchronously in a looped system and in only one direction. Newer RIMM versions run at 1,066MHz or 1,200MHz in addition to the original 800MHz rate and are available in single-channel, 16-bit versions as well as multiple-channel, 32-bit and 64-bit versions for throughputs up to 9.6GBps per module.

A single Rambus memory channel can support up to 32 individual RDRAM devices (the RDRAM chips), and more if buffers are used. Each individual chip is serially connected to the next on a package called a Rambus inline memory module (RIMM), but all memory transfers are done between the memory controller and a single device, not between devices.

The individual RDRAM chips are contained on RIMMs, and a single channel typically has three RIMM sockets. The RDRAM memory bus is a continuous path through each device and module on the bus, with each module having input and output pins on opposite ends.

There fore, any RIMM sockets not containing a RIMM must then be filled with a continuity module to ensure that the path is completed. The signals that reach the end of the bus are terminated on the motherboard. Each RDRAM chip on a RIMM1600 essentially operates as a standalone module sitting on the 16-bit data channel.

Internally, each RDRAM chip has a core that operates on a 128-bit wide bus split into eight 16-bit banks running at 100MHz. In other words, every 10ns (100MHz) each RDRAM chip can transfer 16 bytes to and from the core. This internally wide yet externally narrow high-speed interface is the key to RDRAM. Other improvements to the design include separating control and data signals on the bus.

Independent control and address buses are split into two groups of pins for row and column commands, while data is transferred across the 2-byte wide data bus. The actual memory bus clock runs at 400MHz; however, data is transferred on both the falling and rising edges of the clock signal, or twice per clock pulse.

The falling edge is called an even cycle, and the rising edge is called an odd cycle. Complete memory bus synchronization is achieved by sending packets of data beginning on an even cycle interval. The overall wait before a memory transfer can begin (latency) is only one cycle, or 2.5ns maximum.

An RDRAM data packet always begins on an even (falling) transition for synchronization purposes. The architecture also supports multiple, simultaneous interleaved transactions in multiple separate time domains. Therefore, before a transfer has even completed, another can begin.

Another important feature of RDRAM is that it is a low-power memory system. The RIMMs themselves as well as the RDRAM devices run on only 2.5 volts and use low-voltage signal swings from 1.0V to 1.8V, a swing of only 0.8V total. RDRAMs also have four power-down modes and can automatically transition into standby mode at the end of a transaction, which offers further power savings.

As discussed, RDRAM chips are installed in modules called RIMMs. A RIMM is similar in size and physical form to current DIMMs, but they are not interchangeable. RIMMs are available in module sizes up to 1GB or more and can be added to a system one at a time because each individual RIMM technically represents multiple banks to a system.

They have to be added in pairs if your motherboard implements dual-channel RDRAM and you are using 16-bit wide RIMMs. An RDRAM memory controller with a single Rambus channel supports up to three RIMM modules according to the design. However, most motherboards implement only two modules per channel to avoid problems with signal noise.

RIMMs are available in three primary speed grades, with three different width versions in each grade. The 16-bit versions are usually run in a dual-channel environment, so they have to be installed in pairs, with each one of the pair in a different set of sockets.

Each set of RIMM sockets on such boards is a channel. The 32- and 64-bit versions incorporate multiple channels within a single device, and as such they are designed to be installed individually, eliminating the requirement for matched pairs.

When Intel initially threw its weight behind the Rambus memory, it seemed destined to be a sure thing for success. Unfortunately, technical delays in the chipsets caused the supporting motherboards to be significantly delayed, and with few systems to support the RIMMs, most memory manufacturers went back to making SDRAM or shifted to DDR SDRAM instead.

This caused the remaining available RIMMs being manufactured to be originally priced three or more times that of a comparatively sized DIMM. More recently the cost for RDRAM RIMMs has come down to approximately that of DDR SDRAM, but by the time that happened, Intel had shifted all future chipset development to support only DDR and DDR2 memory.

As I've stated many times, one of the main considerations for memory is that the throughput of the memory bus should match the throughput of the processor bus, and in that area RDRAM RIMMs were originally more suited to the initial Pentium 4 processor systems.

However, with the increases in speed of the Pentium 4 processor bus from 400MHz to 533MHz and then 800MHz and the advent of chipsets supporting dual-channel DDR memory, DDR is currently the best match for the CPU bus speeds of both Intel and AMD processors.

In short, the advent of newer chipsets supporting dual-channel DDR in 2002 has rendered DDR the best choice for both Pentium 4– and Athlon XP–based systems, offering the maximum memory performance possible.